The present invention generally relates to a method of forming a semiconductor layer structure, and more particularly to a method of forming an electrical contact between interconnection (wiring) layers located at different layer levels.
Recently, there has been considerable progress in the development of a sub-micron scale semiconductor device. This remarkable advance in the field of semiconductor devices has, however, encountered unexpected problems.
A decrease in the size of interconnection lines (feature size) decreases the size of a bottom portion of a via contact hole (hereinafter simply referred to a contact hole) for connecting interconnection (wiring) layers located at different layer levels. In addition, the size of the bottom portion of the contact hole is further reduced due to the fact that the material of an interconnection layer is deposited in the contact hole by sputtering. That is, when an aspect ratio (which is a ratio of the depth of a contact hole to the diameter thereof) is great, coverage is deteriorated due to the shadow effect. As is well known, the contact resistance increases with a decrease in the size of a contact which realizes an electrical connection. For this reason, an increase in the contact resistance is a serious problem which must be overcome.
Aluminum is widely used for forming interconnection layers since it is less expensive and has a low resistivity. However, when aluminum is exposed to oxygen and/or water vapor in the air during a time when an interconnection layer is formed, a natural oxide film is easily formed on the surface of the Al interconnection layer. The presence of the natural oxide film on the Al interconnection layer causes an increase in resistance of the Al interconnection layer. When the natural oxide film on the Al interconnection layer is formed in a contact hole having a great aspect ratio, the contact resistance becomes greater than an expected value. From the above-mentioned points of view, there is a need for a method of easily eliminating the natural oxide film on the Al interconnection layer.
Referring to FIGS. 1A and 1B, a conventional method of forming a multilevel interconnection layer structure will now be described. A contact hole 40 is formed in an interlayer insulating film 45 on an Al interconnection layer 42 located at a lower layer level. The interlayer insulating film 45 is made of silicon dioxide (SiO.sub.2), a phosphosilicate glass (PSG) or the like. Then an Al interconnection layer 41 at an upper layer level is grown, as shown in FIG. 1B. In order to realize a good electrical contact between the Al interconnection layers 41 and 42, it is necessary to eliminate a natural oxide film 43 in its entirety from the surface of the Al interconnection layer 42 at the lower layer level.
Conventionally, a dry etching process using argon (Ar) gas is used for eliminating the natural oxide film 43. After eliminating the natural oxide film 43, the upper-layer-level Al interconnection layer 42 is successively grown without exposing a wafer 44 to air so that the Al interconnection layer 42 at the lower layer level is prevented from being oxidized again.
A surface treatment by use of dry etching is carried out for eliminating the natural oxide film 43 on the surface of the Al interconnection layer 42 in its entirety. In actuality, not only the surface of the Al interconnection layer 42 but also the surface of the interlayer insulating film 45 are simultaneously etched. In this case, the following problems take place due to the fact that SiO.sub.2 or the like such as SiO.sub.2 or PSG is etched.
First, SiO.sub.2 materials or the like are scattered, by etching, onto internal elements such as a shield and so on in an etching chamber (not shown). These internal elements are formed of stainless steel or aluminum, which has a thermal expansion ratio different from that of SiO.sub.2 or the like. Thus, adhesion between SiO.sub.2 or the like and the internal elements is not good. For this reason, SiO.sub.2 materials or the like comes off the internal elements, and particles of SiO.sub.2 or the like are generated in the etching chamber.
Second, as the aspect ratio increases, it becomes difficult for SiO.sub.2 materials or the like 40a (FIG. 1C) which comes off an inner wall of the contact hole 40 to fly out of the contact hole 40. Thus, SiO.sub.2 materials or the like 40a are deposited on the exposed surface of the Al interconnection layer 42. The presence of SiO.sub.2 or the like 40a on the exposed surface of the Al interconnection layer 42 causes the exposed surface to be oxidized again or causes a change in quality thereof. This deteriorates the electrical contact between the Al interconnection layers 41 and 42. The two-dotted chain lines in FIG. 1C represent the original surface before SiO.sub.2 or the like is scattered.